The following terminology will be used to distinguish between clock signals, the frequencies of clock signals, and the clock period of such clock signals. Clock signals, such as F.sub.x, are denoted with a signal name starting with a capital F. The frequency of clock F.sub.x is denoted f.sub.x and the clock period of clock F.sub.x is denoted T.sub.x, which is equal to 1/f.sub.x.
FIG. 1 shows a block diagram of a typical frequency synthesizer 20. The synthesizer 20 consists of a phase detector 22, a loop filter 24, a voltage controlled oscillator (VCO) 26 and two frequency dividers 28 and 30. Components 22 through 28 form a conventional phase-locked loop (PLL) 32. When the synthesizer is in lock, the specified output frequency is EQU f.sub.out =N*f.sub.REF =N*f.sub.EXT /M (Eq. 1)
where M and N are the divisors of the frequency dividers 30 and 28, respectively. M and N are typically integers. The reference frequency, f.sub.REF, is generated by dividing an external reference frequency, f.sub.EXT, by M. The specified output frequency, f.sub.OUT, is then synthesized from clock F.sub.REF by means of the phase-locked loop (PLL) 32. The specified output frequency can be adjusted by digitally varying (i.e., programming) the value of N. Therefore, the minimum increment by which f.sub.OUT can be changed, i.e., the resolution of the frequency synthesizer 20, is simply the reference frequency, f.sub.REF.
In applications where the purpose of the phase-locked loop is to generate a clock signal which matches the frequency of the external clock F.sub.EXT, the two frequency dividers 28 and 30 can be eliminated. A typical application for such a circuit is regenerating the clock associated with a received signal, where the frequency of the received signal can vary within a known frequency range.
Traditional voltage-controlled oscillators (VCOs) used in analog phase-locked loops normally require the conversion of an analog voltage to a capacitance, and then the capacitance is used to control the output frequency of an oscillator. This approach is sensitive to input noise, as well as other common mode interferences such as dc offset and supply voltage variation because the frequency controlling element is a single-ended voltage source and the voltage to frequency conversion gain is usually high and non-linear. Put more simply, traditional VCOs have significant problems when used in very high frequency (e.g., over 50 or 100 MHz) phase-locked loops.
Some PLLs use conventional digital controlled oscillators (DCOs) instead of a VCO. However, DCOs require a local clock frequency many times higher than the PLL's operating frequency in order to achieve acceptable phase resolution. Thus the DCO in a PLL with an operating frequency of 100 MHz may need a local clock with frequency higher than 1 GHz, which cannot be achieved using conventional integrated circuits.
The present invention, together with a signed phase-to-frequency converter (also called a waveform synthesizer), replaces the traditional VCO in a PLL. The FCO of the present invention provides a mechanism that can be used to generate output clock signals matching an input signal's frequency, with the FCO using a local clock that is approximately equal to the operating frequency of the PLL. The present invention is especially suitable for high PLL operating frequencies, above 50 MHz.